In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. As the size of CMOS transistors, also referred to as MOSFETs, are scaled down, one of the most important challenges facing a device designer are short channel effects (SCE) in reduced gate length devices. For example, short channel effects that influence the electrical operating characteristics of FET devices include VT rolloff, drain induced barrier lowering (DIBL), subthreshold swing degradation, gate to drain overlap capacitance and current (diode) leakage characteristics. Short channel effects (SCE) are a function of several processing effects including width and depth of S/D regions and S/D region dopant concentration.
For example, since SCE is related to the junction depth (xj), shallower junction depths can improve device operating characteristics. However, an off-setting consideration as junction depths decrease is the increase in the S/D parasitic resistance which has several components including the resistance of the source/drain extension (SDE) region and the resistance of conductive portions over the source/drain regions. As the junction depth decreases to reduce SCE, increased dopant concentrations are required to offset an increase in parasitic resistance to avoid degradation of device performance.
To overcome some of the short channel effects (SCE) as device sizes are scaled down, including leakage current (diode leakage), proposed solutions have included providing raised S/D regions by raising up the S/D contact surface by selective epitaxial silicon growth (SEG) over the S/D contact regions. While diode leakage has been shown to be reduced by this process, other shortcomings remain, including achieving shallower junction depths while preserving low S/D and SDE resistances. For example, gate to drain overlap capacitance is strongly affected by lateral diffusion of the doped S/D and SDE regions, which is increasingly difficult to control by conventional ion implantation and thermal diffusion processes. For example, carrying out a process to form raised S/D structures following doping of the S/D regions contributes an additional thermal process which can undesirably increase the lateral diffusion thereby increasing gate to drain overlap capacitance and degrading device performance.
In addition, ion implantation to form ultra-shallow junctions, for example less than about 300 Angstroms, is increasingly difficult to control. For example higher dopant implant concentrations are required to avoid an increase in parasitic resistances at shallower junction depths. While reducing the ion implant energy may result in shallower junctions, the higher required dopant concentration required contributes to significant semiconductor substrate damage including forming amorphous or disordered lattice regions.
Consequently, in the thermal activation process, or in subsequent thermal processes carried out following ion implantation and activation, localized ion implanted damaged regions experience higher dopant diffusion rates, leading to poorly defined dopant region interfaces, which contributes to both increased junction depths and increased lateral diffusion into the channel region below the gate. As a result, SCE effects are increased, including increased gate to drain overlap capacitance and current leakage thereby degrading device performance and reliability.
There is therefore a continuing need in the MOSFET device design and processing art to develop new device designs and processing methods for forming MOSFET devices to achieved reduced short channel effects (SCE) while avoiding degradation of device performance and reliability.
It is therefore among the objects of the present invention to provide an improved MOSFET device and a process for forming the same to achieved reduced short channel effects (SCE) while avoiding degradation of device performance and reliability, in addition to overcoming other shortcomings of the prior art.